P4C1256L

`V_CC Current (Commercial/Industrial)
- Operating: 70mA/85mA
- CMOS Standby: 100mA/100mA
`Access Times
-55/70 (Commercial or Industrial)
`Single 5 Volts ±10% Power Supply
`Easy Memory Expansion Using CE and OE Inputs
`Common Data I/O
`Three-State Outputs
`Fully TTL Compatible Inputs and Outputs
`Advanced CMOS Technology
`Automatic Power Down
`Packages
-28-Pin 600 mil DIP
-28-Pin 330 mil SOP

The P4C1256L is a 262,144-bit low power CMOS static RAM organized as 32Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply.

Access times of 55 ns and 70 ns are available. CMOS P4C1256L is utilized to reduce power consumption to a low level.

The P4C1256L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling (OE ) while write enable (WE ) remains HIGH. By presenting the address under these conditions, the data of P4C1256L in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW.

Package options for the P4C1256L include 28-pin 600 mil DIP and 28-pin 330 mil SOP packages.