DescriptionThe NN514256 series is a high performance CMOS dynamic random access memory organized as 262,144 words by 4 bits. The NN514256/A series is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operat...
NN514256: DescriptionThe NN514256 series is a high performance CMOS dynamic random access memory organized as 262,144 words by 4 bits. The NN514256/A series is fabricated with advanced CMOS technology and des...
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PinoutDescriptionThe NN5118160ALJ-70 is a high performance CMOS dynamic access memory organized as...
The NN514256 series is a high performance CMOS dynamic random access memory organized as 262,144 words by 4 bits. The NN514256/A series is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at both component and system levels. The NN514256 series features a high speed page mode operation in which a high speed read, write or read-write is performed on any column address along a row address. An extremely short row address capture time and an asynchronous column address decoder relax the timing constraints associated with address multiplexing. The outputs of NN514256 are tri-stated by (`IS which, ln essence, acts as an output enable independent of RAS with very fast (T to output access time. Refresh is accomplished by performing R7-(S only refresh cycles, hidden refresh cycles, CF before RAS refresh cycles, or normal read or write cycles on the 512 address combinations of AO to AS during a 8 ms period. Multiplexed address inputs permit the NN514256/A series to be packaged in a standard 20-pin plastic DIP, 26- pin plastic SOJ, 20-pin plastic ZIP and 24 pin TSOP TYPE l. The package sizes of NN514256 provide high system bit densities and are compatible with widely available automated testin and insertion equipment. System level features include sin le power supply of 5V it 0% tolerance and direct interface with high performance TTL logic families.
The features of NN514256 can be summarized as (1)262.144 4 bit organization; (2)single 5V :10% power supply; (3)performance ranges; (4)fast page made operation; (5)low power operation; (6)low standby current (CMOS level inputs), standard 1mA, version 50A; (7)512 refresh cycles, standard distributed across 8ms, version distributed across 128ms; (8)all inputs/outputs and clocks fully TTL and CMOS compatible; (9)refresh modes RAS only, CAS before RAS, hidden refresh; (10)high reliability packages: plastic 20pin DIP (P20DP-1A0), plastic 20pin ZIP (P20ZP-250), plastic 26pin SOJ (P26SJ-ZA6), plastic 24pin TSOP TYPE I(P24TV-5B4).
The absolute maximum ratings of NN514256 are (1)voltage on any pin relative to VSS VIN,VOUT: -1 to 7V; (2)voltage on VCC relative to VSS VCC: -1 to 7V; (3)storage temperature (plastic) Tstg: -55 to +125°C; (4)power dissipation PD: 1.0W; (5)ambient operating temperature Ta: 0 to +70°C; (6)short circuit output current IOUT: 50mA.(Permanent device dama e can occur if absolute maximum ratings are exceeded. Functional operation should restricted to the condltlons as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.)