NN514105A

The NN514105A series is a high performance CMOS dynamic random access memory organized as 4,194,304 words by 1-bits.The NN514105A series is fabricated with advanced CMOS technology and designed with innoveative design techniques resulting in high speed,extremely low power and wide operating margins at both componebt abd system levels.

The NN514105A series features an EDO(Hyper page) mode operating in which a high speed read,write or read-write is performed on any column address along a row address.An extremely short row address capture time and an asynchronous column decoder relax the timing constraints associated with address multiplexing.

Refresh of NN514105A is accomplished by performing RAS only refresh cycles,hidden refresh cycles,CAS before RAS refresh cycles,or normal read or write cycles on the 1,024 address combinations of A0 to A10 during a 16 ms period.

Mulitiplexed address input permit The NN514105A series to be package in a standard 26-pin plastic SOJ,26 pin TSOP TYPE .The package size provide high system include single power supply of 5V±10% tolerance and direct interface with high performance TTL logic families.

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