Features: • High speed parallel latches• Live insertion/extraction permitted• Extra data width for wide address/data paths or buses carrying parity• Power-up 3-State• Power-up reset• Ideal where high speed, light loading, or increased fan-in are required with MO...
MB2841: Features: • High speed parallel latches• Live insertion/extraction permitted• Extra data width for wide address/data paths or buses carrying parity• Power-up 3-State• P...
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SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
VCC |
DC supply voltage |
|
0.5 to +7.0 |
V |
IIK |
DC input diode current |
VI < 0 |
18 |
mA |
VI |
DC input voltage3 |
|
1.2 to +7.0 |
V |
IOK |
DC output diode current |
VO < 0 |
50 |
mA |
VOUT |
DC output voltage3 |
output in Off or High state |
0.5 to +5.5 |
V |
IOUT |
DC output current |
output in Low state |
128 |
mA |
Tstg |
Storage temperature range |
|
65 to 150 |
°C |
The MB2841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity.
The MB2841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (nOE) is Low. When nOE of MB2841 is High the output is in the High-impedance state.