Features: ` Supply Voltage
VCC = 1.7 to 1.95V core supply voltage
VCCQ = 1.7 to 1.95V for I/O buffers
` User-selectable Operating Modes
Asynchronous Modes: Random Read, and Write, Page Read
Synchronous Modes: NOR-Flash, Full Synchronous (Burst Read and Write)
` Asynchronous Random Read
Access Time: 70ns
` Asynchronous Page Read
Page Size: 4, 8 or 16 Words
Subsequent Read Within Page: 20ns
` Burst Read
Fixed Length (4, 8, 16 or 32 Words) or Continuous
Maximum Clock Frequency: 104MHz
Output delay: 7ns at 104MHz
` Low Power Consumption
Active Current: < 25mA
Standby Current: 140A
Deep Power-Down Current: < 10A
` Low Power Features
Partial Array Self-Refresh (PASR)
Deep Power-Down (DPD) Mode
Automatic Temperature-compensated Self-Refresh
` Operating Temperature
30°C to +85°CSpecificationsStressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
| Symbol |
Parameter |
Min |
Max |
Unit |
| TA |
Ambient Operating Temperature |
30 |
+85 |
°C |
| TSTG |
Storage Temperature |
55 |
150 |
°C |
| VCC |
Core Supply Voltage |
0.2 |
2.45 |
V |
| VCCQ |
Input/Output Buffer Supply Voltage |
0.2 |
2.45 |
V |
| VIO |
Input or Output Voltage |
0.2 |
2.45 |
V |
DescriptionThe M69KB096AB is a 64 Mbit (67,108,864 bit) PSRAM, organized as 4,194,304 Words by 16 bits. It uses a high-speed CMOS DRAM technology implemented using a one transistor-per-cell topology that achieves bigger array sizes. It provides a high-density solution for low-power handheld applications.
The M69KB096AB is supplied by a 1.7 to 1.95V supply voltage range.
The PSRAM interface supports various operating modes: Asynchronous Random Read and Write, Asynchronous Page Read and Synchronous mode that increases read/write speed. In Asynchronous Random Read mode, the M69KB096AB is compatible with low power SRAMs.
In Asynchronous Page mode the device has much shorter access times within the page that make it is compatible with the industry standard PSRAMs.
Two types of Synchronous modes are available:
·Flash-NOR: the device operates in Synchronous mode for read operations and Asynchronous mode for write operations.
·Full Synchronous: the device supports Synchronous transfers for both read and write operations.
The M69KB096AB features three configuration registers:
·Two user-programmable registers used to define the device operation: the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR).
·A read-only Device ID Register (DIDR) containing device identification.
The Bus Configuration Register (BCR) indicates how the device interacts with the system memory bus. The Refresh Configuration Register (RCR) is used to control how the memory array refresh is performed. At Power-Up, these registers are automatically loaded with default settings and can be updated any time during normal operation.
PSRAMs are based on the DRAM technology, but have a transparent internal self-refresh mechanism that requires no additional support from the system memory microcontroller.
To minimize the value of the Standby current during self-refresh operations, the M69KB096AB includes three system-accessible mechanisms configured via the Refresh Configuration Register (RCR):
·Partial Array Self Refresh (PASR) performs a limited refresh of the part of the PSRAM array that contains essential data.
·Deep Power-Down (DPD) mode completely halts the refresh operation. It is used when no essential data is being held in the device.
·Automatic Temperature Compensated Self Refresh (TCSR) adjusts the refresh rate according to the operating temperature.
M69KB096AB Data Sheet
