Features: ` SUPPLY VOLTAGE
VCC = 1.7 to 1.95V core supply voltage
VCCQ = 1.7 to 3.3V for I/O buffers
` ASYNCHRONOUS MODES
Asynchronous Random Read: 70ns and 85ns access time
Asynchronous Write
Asynchronous Page Read Page Size: 16 words Subsequent read within page: 20ns
` SYNCHRONOUS BURST READ AND WRITE MODES
Burst Write in Continuous Mode
Burst Read: Fixed Length (4, 8, or 16 Words) or Continuous mde
Maximum Clock Frequency: 66MHz,80MHz
Burst initial latency: 50ns (4 clock cycles) at 80MHz
Output delay: 9ns at 80MHz
` BYTE CONTROL BY LB/UB
` LOW POWER CONSUMPTION
Asynchronous Random Read Mode:< 25mA
Asynchronus Page Read Mode (subsequent read operations): < 15mA
Synchronous Burst Read Initial access: < 35mA
Continuous Burst Read: < 15mA
Standby Current: 120A
Deep Power-Down Current: 10A (typ)
` LOW POWER FEATURES
Temperature Compensated Refresh (TCR)
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
` OPERATING TEMPERATURE
30°C to +85°CSpecificationsStressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
| Symbol |
Parameter |
Min |
Max |
Unit |
| TA |
Ambient Operating Temperature |
30 |
85 |
°C |
| TSTG |
Storage Temperature |
55 |
150 |
°C |
| VCC |
Core Supply Voltage |
0.2 |
2.45 |
V |
| VCCQ |
Input/Output Buffer Supply Voltage |
0.2 |
4.0 |
V |
| VIO |
Input or Output Voltage |
0.5 |
4.0 or
VCCQ+0.3
(1) |
V |
Note: 1. Whichever is the lower.
DescriptionThe M69KB096AA is a 64 Mbit (67,108,864 bit) PSRAM, organized as 4,194,304 words by 16 bits. The memory array is implemented using a one transistor-per-cell topology, to achieve bigger array sizes.
This device is a high-speed CMOS, dynamic random- access memory. It provides a high-density solution for low-power handheld applications. The M69KB096AA includes the industry standard Flash memory burst mode that dramatically increases read/write over that of other low-power SRAM or PSRAMs.
The PSRAM interface supports both asynchronous and burst-mode transfers. Page mode accesses are also included as a bandwidthenhancing extension to the asynchronous read protocol. PSRAMs are based on the DRAM technology, but have a transparent internal self-refresh mechanism that requires no additional support from the system memory controller, and has no significant impact on the device read/write performance.
The M69KB096AA has two configuration registers, accessible to the user to define the device operation: the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR). The Bus Configuration Register (BCR) indicates how the device interacts with the system memory bus. Overall, it is identical to its counterpart in burst-mode Flash memory devices.
The Refresh Configuration Register (RCR) is used to control how the memory array refresh is performed. At power-up, these registers are automatically loaded with default settings and can be updated any time during normal operation.
To minimize the value of the standby current during self-refresh operations, the M69KB096AA includes three system-accessible mechanisms configured via the Refresh Configuration Register (RCR):
·The Temperature Compensated Refresh (TCR) is used to adjust the refresh rate according to the operating temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby.
·The Partial Array Refresh (PAR) performs a limited refresh of the part of the PSRAM array that contains essential data. ·The Deep Power-Down (DPD) mode completely halts the refresh operation. It is used when no essential data is being held in the device.
M69KB096AA Data Sheet
