M54/M74HC192

Features: .HIGH SPEEDfMAX = 54 MHz (TYP.) AT VCC = 5 V .LOWPOWER DISSIPATIONICC = 4 mA (MAX.) AT TA = 25 °C .HIGH NOISE IMMUNITYVNIH= VNIL= 28%VCC (MIN.) .OUTPUT DRIVE CAPABILITY10 LSTTL LOADS .SYMMETRICAL OUTPUT IMPEDANCE|IOH| = IOL = 4 mA (MIN.) .BALANCEDPROPAGATION DELAYStPLH = tPHL .WIDE OPERA...

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SeekIC No. : 004405689 Detail

M54/M74HC192: Features: .HIGH SPEEDfMAX = 54 MHz (TYP.) AT VCC = 5 V .LOWPOWER DISSIPATIONICC = 4 mA (MAX.) AT TA = 25 °C .HIGH NOISE IMMUNITYVNIH= VNIL= 28%VCC (MIN.) .OUTPUT DRIVE CAPABILITY10 LSTTL LOADS .SYMM...

floor Price/Ceiling Price

Part Number:
M54/M74HC192
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

.HIGH SPEED
fMAX = 54 MHz (TYP.) AT VCC = 5 V
.LOWPOWER DISSIPATION
ICC = 4 mA (MAX.) AT TA = 25 °C
.HIGH NOISE IMMUNITY
VNIH= VNIL= 28%VCC (MIN.)
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
.BALANCEDPROPAGATION DELAYS
tPLH = tPHL
.WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
.PIN AND FUNCTION COMPATIBLE WITH 54/74LS192-193



Pinout

  Connection Diagram  Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Source Sink Current Per Output Pin ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
PD Power Dissipation 500 (*) mW
Tstg Storage Temperature -65 to +150 oC
TL Lead Temperature (10 sec) 300 oC



Description

    TheM54/74HC192/193 are ahigh speedCMOSSYNCHRONOUSUP/DOWN DECADE COUNTERS fabricated in silicon gate C2MOStechnology. They have thesame high speedperformance ofLSTTL combined with true CMOS low power consumption.

    The counter of M54/74HC192/193  has two separate clock inputs, an UP COUNT input and a DOWN COUNT input. All outputs of the flip-flop are simultaneously triggered on the low to high transition of either clockwhilethe other input isheld high. The direction of counting is determined by which input is clocked. This counter may be preset by entering the
desired data on the DATA A, DATA B, DATA C, and DATA D input.When the LOADinput is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as divide-by-n counters by modifying the count length with the preset inputs.

   In addition the counter of M54/74HC192/193  can also be cleared. This is accomplished by inputting a high on the CLEAR input.All 4 internal stages are set to low independently of either COUNT input. Both aBORROWandCARRY output areprovided toenable cascading of bothupand down counting functions. The BORROW output produces a negative going pulse when thecounter underflows and the CARRY outputs a pulse when the counter overflows. The counter can be cascaded by connecting the CARRY and BORROWoutputs of one device to the COUNT UP and COUNTDOWN inputs, respectively, of the next device. All inputs are equipped with protection circuits against static discharge and transient excess voltage.


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