M54/74HC40102

Features:

HIGH SPEED fMAX = 40 MHz (TYP.) at VCC = 5V 
LOWPOWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 °C
HIGH NOISE IMMUNITY VNIH= VNIL= 28%VCC(MIN.)
OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.)
BALANCEDPROPAGATION DELAYS tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V
PIN AND FUNCTION COMPATIBLE WITH 40102B/40103B

Specifications

Symbol	Parameter	Value	Unit
VCC	Supply Voltage	-0.5 to +7	V
VI	DC Input Voltage	-0.5 to VCC + 0.5	V
VO	VO DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	± 20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Source Sink Current Per Output Pin	± 25	mA
ICC or IGND	DC VCC or Ground Current	± 50	mA
PD	Power Dissipation	500 (*)	mA
Tstg	Storage Temperature	-65 to +150	oC
TL	Lead Temperature (10 sec)	300	oC

Description

The M54/74HC40102/40103 are high speed CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

The HC40102, and HC40103 consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The HC40102 is configured as two cascaded 4-bit BCD counters, and the HC40103 contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to itsmaximum count, and for presetting the counter either synchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE) input is high. The CARRY-OUT/ZERO-DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the J input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input.