Features: *.HIGH SPEED fMAX = 50 MHz (TYP.) AT VCC = 5 V *LOWPOWER DISSIPATION ICC = 4 mA (MAX.) AT 25 °C *OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS *BALANCEDPROPAGATION DELAYS tPLH = tPHL *SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) *COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.); VIL = 0.8V (...
M54/74HCT160/161: Features: *.HIGH SPEED fMAX = 50 MHz (TYP.) AT VCC = 5 V *LOWPOWER DISSIPATION ICC = 4 mA (MAX.) AT 25 °C *OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS *BALANCEDPROPAGATION DELAYS tPLH = tPHL *SYMMETRICAL...
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Features: .HIGHSPEED fMAX=70MHz(TYP.)atVCC=5V.LOW POWER DISSIPATION ICC=4mA(MAX.)atTA=25oC.HIGH NO...
Features: .HIGHSPEED fMAX=70MHz(TYP.)atVCC=5V.LOW POWER DISSIPATION ICC=4mA(MAX.)atTA=25oC.HIGH NO...
Features: HIGH SPEED fMAX = 40 MHz (TYP.) at VCC = 5V LOWPOWER DISSIPATION ICC = 4 mA (MAX.) at ...
Symbol | Parameter | Value | Unit |
VCC | Supply Voltage | -0.5 to +7 | V |
VI | DC Input Voltage | -0.5 to VCC + 0.5 | V |
VO | DC Output Voltage | -0.5 to VCC + 0.5 | V |
IIK | DC Input Diode Current | ± 20 | mA |
IOK | DC Output Diode Current | ± 20 | mA |
IO | DC Output Source Sink Current Per Output Pin | ± 25 | mA |
ICCor IGND | DC VCC or Ground Current | ± 50 | mA |
PD | Power Dissipation | 500 (*) | mW |
Tstg | Storage Temperature | -65 to +150 | oC |
TL | Lead Temperature (10 sec) | 300 | oC |
M54/74HCT160 Decade, Asynchronous Clear
M54/74HCT161 Binary, Asynchronous Clear
M54/74HCT162 Decade, Synchronous Clear
M54/74HCT163 Binary, Synchronous Clear
The M54/74HCT160, 161, 162 and 163 are high speed CMOS SYNCHRONOUS PRESETTABLE COUNTERS fabricated with silicon gate C2MOS technology. They have the same high speed operation similar to equivalent LSTTL while maintaining the CMOSlow power dissipation. The M54/74HCT160/162 are BCDDecade counters and the M54/74HCT161/163 are 4 bit binary
counters. The CLOCK input is active on the rising edge. Both LOAD and CLEAR inputs are active Low.
Presetting of all four IC's is synchronous on the rising edge of the CLOCK. The function on the M54/74HCT162/163 is synchronous to CLOCK, while the M54/74HCT160/161 counters are cleared asynchronously. Two enable inputs (TE and PE) andCARRYoutput are provided to enable easycascading of counters, which facilities easy implementation of N-bit counters without using external gates. This integrated circuit has input and output characteristicsthat are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. All inputs are equipped with