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M36L0T7050T0

Features: ` MULTI-CHIP PACKAGE 1 die of 128Mbit (8Mx16, Multiple Bank, Multi-level, Burst) Flash Memory 1 die of 32Mbit (2Mx16) Pseudo SRAM` SUPPLY VOLTAGE VDDF = 1.7 to 2V VDDP = VDDQ = 2.7 to 3.3V VPP = 9V for fast program (12V tolerant)` ELECTRONIC SIGNATURE Manufacturer Code: 20h Device...

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SeekIC No. : 004404851 Detail

M36L0T7050T0: Features: ` MULTI-CHIP PACKAGE 1 die of 128Mbit (8Mx16, Multiple Bank, Multi-level, Burst) Flash Memory 1 die of 32Mbit (2Mx16) Pseudo SRAM` SUPPLY VOLTAGE VDDF = 1.7 to 2V VDDP = VDDQ = 2.7 to ...

M36L0T7050T0 Data Sheet

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Part Number:
M36L0T7050T0
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

` MULTI-CHIP PACKAGE
   1 die of 128Mbit (8Mx16, Multiple Bank, Multi-level, Burst) Flash Memory
   1 die of 32Mbit (2Mx16) Pseudo SRAM
` SUPPLY VOLTAGE
   VDDF = 1.7 to 2V
   VDDP = VDDQ = 2.7 to 3.3V
   VPP = 9V for fast program (12V tolerant)
` ELECTRONIC SIGNATURE
   Manufacturer Code: 20h
   Device Code (Top Flash Configuration) M36L0T7050T0: 88C4h
   Device Code (Bottom Flash Configuration) M36L0T7050B0: 88C5h
` PACKAGE
   Compliant with Lead-Free Soldering Processes
   Lead-Free Versions
FLASH MEMORY
` SYNCHRONOUS / ASYNCHRONOUS READ
   Synchronous Burst Read mode: 50MHz
   Asynchronous Page Read mode
   Random Access: 90ns
` SYNCHRONOUS BURST READ SUSPEND
` PROGRAMMING TIME
   10µs typical Word program time using Write to Buffer and Program
` MEMORY ORGANIZATION
   Multiple Bank Memory Array: 8 Mbit Banks
   Parameter Blocks (Top or Bottom location)
` DUAL OPERATIONS
   program/erase in one Bank while read in others
   No delay between read and write operations
` SECURITY
   64 bit unique device number
   2112 bit user programmable OTP Cells
` BLOCK LOCKING
   All blocks locked at power-up
    Any combination of blocks can be locked with zero latency
    WP for Block Lock-Down
   Absolute Write Protection with VPP = VSS
` COMMON FLASH INTERFACE (CFI)
` 100,000 PROGRAM/ERASE CYCLES per BLOCK
PSRAM
` ACCESS TIME: 70ns
` LOW STANDBY CURRENT: 100µA
` DEEP POWER-DOWN CURRENT: 10µA
` BYTE CONTROL: UBP/LBP
` PROGRAMMABLE PARTIAL ARRAY
` 8 WORD PAGE ACCESS CAPABILITY: 18ns
` POWER-DOWN MODES
   Deep Power-Down
   4 Mbit Partial Array Refresh
   8 Mbit Partial Array Refresh
   16 Mbit Partial Array Refresh


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
Min
Max
TA
 Ambient Operating Temperature
25
85
TBIAS
 Temperature Under Bias
25
85
TSTG
 Storage Temperature
55
125
TLEAD
 Lead Temperature during Soldering
(1)
VIO
 Input or Output Voltage
0.5
3.6
V
VDDF
 Flash Memory Core Supply Voltage
0.2
2.5
V
VDDF, VDDP
 PSRAM and Input/Output Supply Voltages
0.2
3.6
V
VPPF
 Flash Program Voltage
0.2
14
V
IO
 Output Short Circuit Current
100
mA
tVPPFH
 Time for VPPF at VPPFH
100
hours
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ®
              7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
              2002/95/EU.


Description

The M36L0T7050T0 and M36L0T7050B0 combine two memory devices in a Multi-Chip Package: Ma 128-Mbit, Multiple Bank Flash memory, the M30L0T7000T0 or M30L0T7000B0, and a 32-Mbit PseudoSRAM, the M69AW048B. Recommended operating conditions do not allow more than one memory to be active at the same time.

The memory of M36L0T7050T0 and M36L0T7050B0 is offered in a Stacked TFBGA88 (8x10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the packages of M36L0T7050T0 and M36L0T7050B0 are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive.

All packages of M36L0T7050T0 and M36L0T7050B0 are compliant with Lead-free soldering processes.

The memory of M36L0T7050T0 and M36L0T7050B0 is supplied with all the bits erased (set to '1').




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