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M36L0R8060T0

Features: ` MULTI-CHIP PACKAGE 1 die of 256 Mbit (16Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory 1 die of 64 Mbit (4Mb x16) Pseudo SRAM` SUPPLY VOLTAGE VDDF = VCCP = VDDQ = 1.7 to 1.95V VPP = 9V for fast program` ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code M36L0R80...

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SeekIC No. : 004404848 Detail

M36L0R8060T0: Features: ` MULTI-CHIP PACKAGE 1 die of 256 Mbit (16Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory 1 die of 64 Mbit (4Mb x16) Pseudo SRAM` SUPPLY VOLTAGE VDDF = VCCP = VDDQ = 1.7 to 1.95...

M36L0R8060T0 Data Sheet

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Part Number:
M36L0R8060T0
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` MULTI-CHIP PACKAGE
   1 die of 256 Mbit (16Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory
   1 die of 64 Mbit (4Mb x16) Pseudo SRAM
` SUPPLY VOLTAGE
   VDDF = VCCP = VDDQ = 1.7 to 1.95V
   VPP = 9V for fast program
` ELECTRONIC SIGNATURE
   Manufacturer Code: 20h
   Top Device Code M36L0R8060T0: 880Dh
   Bottom Device Code M36L0R8060B0: 880Eh
` PACKAGE
   Compliant with Lead-Free Soldering Processes
   Lead-Free Versions
FLASH MEMORY
` SYNCHRONOUS / ASYNCHRONOUS READ
   Synchronous Burst Read mode: 54MHz
   Asynchronous Page Read mode
   Random Access: 85ns
` SYNCHRONOUS BURST READ SUSPEND
` PROGRAMMING TIME
   10µs typical Word program time using Buffer Enhanced Factory Program command
` MEMORY ORGANIZATION
   Multiple Bank Memory Array: 16 Mbit Banks
   Parameter Blocks (Top or Bottom location)
` DUAL OPERATIONS
   program/erase in one Bank while read in others
   No delay between read and write operations
` SECURITY
   64 bit unique device number
   2112 bit user programmable OTP Cells
` BLOCK LOCKING
   All blocks locked at power-up
   Any combination of blocks can be locked with zero latency
   WPF for Block Lock-Down
   Absolute Write Protection with VPPF = VSS
` COMMON FLASH INTERFACE (CFI)
` 100,000 PROGRAM/ERASE CYCLES per BLOCK
PSRAM
` ACCESS TIME: 70ns
` ASYNCHRONOUS PAGE READ
   Page Size: 16 words
   Subsequent read within page: 20ns
` LOW POWER FEATURES
   Temperature Compensated Refresh (TCR)
   Partial Array Refresh (PAR)
   Deep Power-Down (DPD) Mode
` SYNCHRONOUS BURST READ/WRITE


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
Min
Max
TA
 Ambient Operating Temperature
25
85
TBIAS
 Temperature Under Bias
25
85
TSTG
 Storage Temperature
65
125
TLEAD
 Lead Temperature during Soldering
(1)
VIO
 Input or Output Voltage
0.5
2.75
V
VDDF, VDDQ,
VCCP
 Core and Input/Output Supply Voltages
0.2
2.45
V
VPPF
 Flash Program Voltage
0.2
10
V
IO
 Output Short Circuit Current
100
mA
tVPPFH
 Time for VPPF at VPPFH
100
hours
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ®
              7191395  specification, and the European directive on Restrictions on Hazardous Substances
              (RoHS) 2002/95/EU.


Description

The M36L0R8060T0 and M36L0R8060B0 combine two memory devices in a Multi-Chip Package: a 256-Mbit, Multiple Bank Flash memory, the M30L0R8000T0 or M30L0R8000B0, and a 64- Mbit PseudoSRAM, the M69KR096A. Recommended operating conditions do not allow more than one memory to be active at the same time.

The memory M36L0R8060T0 and M36L0R8060B0 is offered in a Stacked TFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the packages of M36L0R8060T0 and M36L0R8060B0 are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes.

The memory of M36L0R8060T0 and M36L0R8060B0 is supplied with all the bits erased (set to '1').




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