M28W640ECB

Features:

`SUPPLY VOLTAGE
V<sub>DD</sub> = 2.7V to 3.6V Core Power Supply
V<sub>DDQ</sub>= 1.65V to 3.6V for Input/Output
V<sub>PP</sub> = 12V for fast Program (optional)
`ACCESS TIME: 70, 85, 90,100ns
`PROGRAMMING TIME:
10s typical
Double Word Programming Option
Quadruple Word Programming Option
`COMMON FLASH INTERFACE
`MEMORY BLOCKS
Parameter Blocks (Top or Bottom location)
Main Blocks
`BLOCK LOCKING
All blocks locked at Power Up
Any combination of blocks can be locked
WP for Block Lock-Down
`SECURITY
128 bit user Programmable OTP cells
64 bit unique device identifier
`AUTOMATIC STAND-BY MODE
`PROGRAM and ERASE SUSPEND
`100,000 PROGRAM/ERASE CYCLES per BLOCK
`ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Top Device Code, M28W640ECT: 8848h
Bottom Device Code, M28W640ECB: 8849h


Pinout




Specifications

Symbol	Parameter	Value		Unit
		Min	Max
TA	Ambient Operating Temperature (1)	40	85	°C
TBIAS	Temperature Under Bias	40	125	°C
TSTG	Storage Temperature	55	155	°C
VIO	Input or Output Voltage	0.6	VDDQ+0.6	V
VDD, VDDQ	Supply Voltage	0.6	4.1	V
VPP	Program Voltage	0.6	13	V

Description

The M28W640ECB is a 64 Mbit (4 Mbit x 16) nonvolatile Flash memory that can be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 2.7V to 3.6V V_DD supply for the circuitry and a 1.65V to 3.6V V_DDQ supply for the Input/Output pins. An optional 12V V_PP power supply is provided to speed up customer programming.

The device features an asymmetrical blocked architecture. The M28W640EC has an array of 135 blocks: 8 Parameter Blocks of 4 KWord and 127 Main Blocks of 32 KWord. M28W640ECT has the Parameter Blocks at the top of the memory address space while the M28W640ECB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5, Block Addresses.

The M28W640ECB features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP ? VPPLK all blocks are protected against program or erase. All blocks are locked at Power Up.

Each block M28W640ECB can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a 192 bit Protection Register to increase the protection of a system design. The Protection Register is divided into a 64 bit segment and a 128 bit segment. The 64 bit segment contains a unique device number written by ST, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. Figure 6, shows the Protection Register Memory Map.

Program and Erase commands M28W640ECB are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.