LH28F800SU

• User-Configurable x8 or x16 Operation
• User-Selectable 3.3 V or 5 V VCC
• 5 V Write/Erase Operations (5 V VPP)
No Requirement for DC/DC Converter to Write/Erase
• 70 ns Maximum Access Time
• Minimum 2.7 V Read capability
160 ns Maximum Access Time (V_CC = 2.7 V)
• 16 Independently Lockable Blocks
• 0.32 MB/sec Write Transfer Rate
• 100,000 Erase Cycles per Block
• Revolutionary Architecture
Pipelined Command Execution
Write During Erase
Command Superset of Sharp LH28F008SA
• 5 A (TYP.) I_CC in CMOS Standby
• 1 A (TYP.) Deep Power-Down
• State-of-the-Art 0.55 m ETOX™ Flash Technology
• 56-Pin, 1.2 mm * 14 mm * 20 mm TSOP (Type I) Package

    The LH28F800SU is a high performance 8M (8,388,608 bit) block erasable non-volatile random access memory organized as either 512K × 16 or 1M × 8. The LH28F800SU includes sixteen 64K (65,536) blocks or sixteen 32-KW (32,768) blocks. A chip memory map is shown in Figure 3.

    The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use.

    Among the significant enhancements of the LH28F800SU:
• 5 V Write/Erase Operation (5 V V_PP)
• 3.3 V Low Power Capability (2.7 V V_CC Read)
• Improved Write Performance
• Dedicated Block Write/Erase Protection

    A 3/5 input pin reconfigures the device internally for optimized 3.3 V or 5.0 V read/write operation.