LH28F016LL

Absolute Maximum Ratings*
Temperature under bias ......................... 0 to +80
Storage temperature ......................... -65 to +125
V_CC = 3.3 V ±0.3 V Systems4

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum voltage on input/output pins is V_CC + 0.5 V which, during transitions, may overshoot to V_CC + 2.0 V for periods < 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.

The LH28F016LL is a high performance 16M (16,777,216 bit) block erasable non-volatile random access memory organized as either 1M * 16 or 2M x 8. The LH28F016LL includes thirty-two 64K (65,536) blocks or thirty-two 32-KW (32,768) blocks. A chip memory map is shown in Figure 3.

The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use.

Among the significant enhancements of the LH28F016LL:
• 3 V Write/Erase Operation (3 V V_PP)
• 3 V Low Power Capability
• Improved Write Performance
• Dedicated Block Write/Erase Protection

The LH28F016LL will be available in a 56-pin, 1.2 mm thick * 14 mm * 20 mm TSOP (Type I) package. This form factor and pinout allow for very high board layout densities.

A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte/Word Writes and Block Erase operations to be executed using a Two-Write command sequence to the CUI in the same way as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the basic LH28F008SA command-set to achieve higher write performance and provide additional capabilities. These new commands and features include:
• Page Buffer Writes to Flash
• Command Queuing Capability
• Automatic Data Writes During Erase
• Software Locking of Memory Blocks
• Two-Byte Successive Writes in 8-bit Systems
• Erase All Unlocked Blocks

Writing of memory data is performed in either byte or word increments typically within 9 s, a 15% improvement over the LH28F008SA.

Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve 1,000,000 Block Erase Cycles by providing wear-leveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems and Hard Disk Drive designs.

The LH28F016LL incorporates two Page Buffers of 256 Bytes (128 Words) each to allow page data writes. This feature can improve a system write performance by up to 4.8 times over previous flash memory devices.

All operations are started by a sequence of Write commands to the device. Three Status Registers (described in detail later) and a RY/BY output pin provide information on the progress of the requested operation.

While the LH28F008SA requires an operation to complete before the next operation can be requested, theLH28F016LL allows queuing of the next operation while the memory executes the current operation. This eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. The LH28F016LL can also perform write operations to one block of memory while performing erase of another block.

The LH28F016LL provides user-selectable block locking to protect code or data such as Device Drivers, PCMCIA card information, ROM-Executable O/S or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the LH28F016LL has a master Write Protect pin (WP) which prevents any modifications to memory blocks whose lock-bits are set.