Features: The LH28F008SCRL85 SmartVoltage Flash memory maintains backwards-compatibility with SHARP's 28F008SA. Key enhancements over the 28F008SA include:
*SmartVoltage Technology
*Enhanced Suspend Capabilities
*In-System Block Locking
B0th devices share a compatible pinout, status register, and software command set. These similarities enable a clean upgrade from the 28F008SA to LH28F008SCR-L85. When upgrading, it is important to note the following differences:
*Because of new feature support, the two devices have different device codes. This allows for software optimization. l VPPLK has been lowered from 6.5V to 1.5V to support 3.3V and 5V block erase, byte write, and lock-bit configuration operations. The Vpp voltage transitions to GND is recommended for designs that switch Vpp off during read operation. *To take advantage of SmartVoltage technology, allow Vpp connection to 3.3V or 5V.
1. Block erase, byte write and lock-bit configuratior operations with Vcc<3.OV are not supported.
Internal Vcc and VPP detection Circuit4 automatically configures the device for optimizec read and write operations.
A Command User Interface (CUI) serves as the interface between the system processor and interna operation of the device. A valid command sequence
written to the CUI initiates device automation. Ar internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuratior operations.
A block erase operation erases one of the device`s 64-Kbyte blocks typically within 0.3 s (5V Vcc 12V Vpp) independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block.
Writing memory data is performed in byte increments typically within 6 s (5V Vcc 12V Vpp). Byte write suspend mode enables the system to read data or execute code from any other flash memory array location.
SpecificationsOperating Temperature
During Read, Block Erase, Byte Write
and Lock-Bit Configuration . . . . .0 to +70 (1)
Temperature under Bias . . . . . . -10 to +80
Storage Temperature . . . . . . . .-65 to +125
Voltage On Any Pin
(except Vcc, Vpp and RP#) . . -2.0V to +7.0V(2)
Vcc Supply Voltage . . . . . . . -2.0V to +7.0(2)
Vpp Update Voltage during
Block Erase, Byte Write and
Lock-Bit Configuration . . . . -2.0V to +14.0V(2,3)
RP# Voltage with Respect to
GND during Lock-Bit
Configuration Operations . . -2.0V to +14.0V(2,3)
Output Short Circuit Current . .. . . . . 1 00mA(4)
NOTES:
1. Operating temperature is for commercial temperature product defined by this specification.
2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on Vcc and Vpp pins. During transitions, this level may undershoot to -2.OV for periods <20ns. Maximum DC voltage on input/output pins and Vcc is Vcc+O.5V which, during transitions, may overshoot to Vcc+2.OV for periods <20ns.
3. Maximum DC voltage on Vpp and RP# may overshoot to +14.OV for periods <20ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
DescriptionThis datasheet contains LH28F008SCR-L85 specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F008SCRL85
Flash memory documentation also includes application notes and design tools which are referenced in Section 7.
LH28F008SCR-L85 Data Sheet
