LCK4953

The LCK4953 is a PLL-based clock driver device intended for high-performance clock tree designs.

The LCK4953 is 3.3 V compatible with output frequencies of up to 130 MHz and output skews of 75 ps. The LCK4953 can meet the most demanding timing requirements and employs on-chip voltage regulators to minimize cycle-to-cycle jitter and phase jitter.

The LCK4953 is ideal for use as a zero delay, low skew, fan-out buffer due to its differential LVPECL reference input along with an external feedback input. The MROEB pin of the LCK4953, when driven high, will reset the internal counters and 3-state the output buffers. The LCK4953 has been optimized for zero delay performance.

The LCK4953 is fully 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the ability to drive terminated 50 transmission lines. For seriesterminated 50 lines, each of the LCK4953 outputs can drive two traces giving the device an effective fan-out of 1:18. For the optimum combination of board density and performance, the device is packaged in a 7 mm * 7 mm 32-lead TQFP package.