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KM736FV4021

Features: • 128Kx36 or 256Kx18 Organizations.• 3.3V Core Power Supply.• LVTTL Input and Output Levels.• Differential, PECL Clock Inputs K, K.• Synchronous Read and Write Operation• Registered Input and Registered Output• Internal Pipeline Latches to Suppor...

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SeekIC No. : 004386201 Detail

KM736FV4021: Features: • 128Kx36 or 256Kx18 Organizations.• 3.3V Core Power Supply.• LVTTL Input and Output Levels.• Differential, PECL Clock Inputs K, K.• Synchronous Read and Writ...

KM736FV4021 Data Sheet

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Part Number:
KM736FV4021
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• 128Kx36 or 256Kx18 Organizations.
• 3.3V Core Power Supply.
• LVTTL Input and Output Levels.
• Differential, PECL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm)


Specifications

PARAMETER
SYMBOL
RATING
UNIT
Note
Core Supply Voltage Relative to VSS
VDD
-0.5 to 3.9
V
Output Supply Voltage Relative to VSS
VDDQ
VDD
V
Voltage on any I/O pin Relative to VSS
VTERM
-0.5 to VDD+0.5
V
Maximum Power Dissipation
PD
3
W
Output Short-Circuit Current
IOUT
25
mA
Operating Temperature
TOPR
0 to 70
Storage Temperature
TSTG
-55 to 125



Description

The KM736FV4021 and KM718FV4021 are 4,718,592 bit Synchronous Pipeline Mode SRAM. It is organized as 131,072words of 36 bits(or 262, 144 words of 18 bits)and is implemented in SAMSUNG¢s advanced CMOS technology.

Single differential PECL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.




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