KM732V595A

Features: • Synchronous Operation.• 2 Stage Pipelined operation with 4 Burst.• On-Chip Address Counter.• Self-Timed Write Cycle.• On-Chip Address and Control Registers.• Core Supply Voltage : 3.3V±5%• 5V Tolerant Inputs except I/O Pins• I/O Supply Vo...

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SeekIC No. : 004386190 Detail

KM732V595A: Features: • Synchronous Operation.• 2 Stage Pipelined operation with 4 Burst.• On-Chip Address Counter.• Self-Timed Write Cycle.• On-Chip Address and Control Registers....

floor Price/Ceiling Price

Part Number:
KM732V595A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/6

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Product Details

Description



Features:

• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• Core Supply Voltage : 3.3V±5%
• 5V Tolerant Inputs except I/O Pins
• I/O Supply Voltage : 2.5V+0.4/-0.13V.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear burst.
• Three Chip Enables for simple depth expansion with No Data Contention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A



Pinout

  Connection Diagram


Specifications

PARAMETER
SYMBOL
RATING
UNIT
Voltage on VDD Supply Relative to VSS
VDD
-0.3 to 4.6
V
Voltage on VDDQ Supply Relative to VSS
VDDQ
VDD
V
Voltage on Input Pin Relative to VSS
VIN
-0.3 to 6.0
V
Voltage on I/O Pin Relative to VSS
VIO
-0.3 to VDDQ+0.5
V
Power Dissipation
PD
1.2
W
Storage Temperature
TSTG
-65 to 150
Operating Temperature
TOPR
0 to 70
Storage Temperature Range Under Bias
TBIAS
-10 to 85



Description

The KM732V595A/L is a 1,048,576 bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

It is organized as 32K words of 32bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.

Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals.

Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system¢s burst sequence and are controlled by the burst address advance(ADV) input.

LBO pin is DC operated and determines burst sequence (linear or interleaved).

ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK.

The KM732V595A/L is fabricated using SAMSUNG¢s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.




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