Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe DQS• Four banks operation• Differential clock inputs(CK and CK)• DLL aligns DQ and DQS transition with CK transition• MRS cycle with address key programs-. R...
K4H1G0738C-UC/LB0: Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe DQS• Four banks operation• Differential clock inputs(CK and CK)•...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: * Double-data-rate architecture; two data transfers per clock cycle* Bidirectional data ...
Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirec...
Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirec...
Parameter | Symbol | Value | Unit |
Voltage on any pin relative to Vss | VIN, VOUT | -0.5 ~ 3.6 | V |
Voltage on VDD & VDDQ supply relative to Vss | VDD ,VDDQ | -1.0 ~ 3.6 | V |
Storage temperature | TSTG | -55 ~ +150 | °C |
Power dissipation | PD | 1.5 | W |
Short circuit current | IOS | 50 | mA |
Note :Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
The K4H1G0638C / K4H1G0738C is 1,073,741,824 bits of double data rate synchronous DRAM organized as 4x 67,108,864 / 4x 33,554,432 / 4x 8,388,608 words by 4/ 8bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 266Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.