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K4H1G0638C-UC/LA2

Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe DQS• Four banks operation• Differential clock inputs(CK and CK)• DLL aligns DQ and DQS transition with CK transition• MRS cycle with address key programs-. R...

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SeekIC No. : 004382759 Detail

K4H1G0638C-UC/LA2: Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe DQS• Four banks operation• Differential clock inputs(CK and CK)•...

K4H1G0638C-UC/LA2 Data Sheet

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Part Number:
K4H1G0638C-UC/LA2
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe DQS
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Pb-Free package
• RoHS compliant


Pinout

Connection Diagram


Specifications

Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V
Voltage on VDD & VDDQ supply relative to Vss VDD ,VDDQ -1.0 ~ 3.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1.5 W
Short circuit current IOS 50 mA

Note :Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.




Description

The K4H1G0638C / K4H1G0738C is 1,073,741,824 bits of double data rate synchronous DRAM organized as 4x 67,108,864 / 4x 33,554,432 / 4x 8,388,608 words by 4/ 8bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 266Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.




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