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ICSSSTVF16859

Features: • Differential clock signals• Meets SSTL_2 signal data• Supports SSTL_2 class I specifications on outputs• Low-voltage operation - VDD = 2.3V to 2.7V• Available in 64 pin TSSOP and 56 pin MLF packagesApplication• DDR Memory Modules: - DDRI (PC1600, PC2...

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SeekIC No. : 004371383 Detail

ICSSSTVF16859: Features: • Differential clock signals• Meets SSTL_2 signal data• Supports SSTL_2 class I specifications on outputs• Low-voltage operation - VDD = 2.3V to 2.7V• Availab...

ICSSSTVF16859 Data Sheet

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Part Number:
ICSSSTVF16859
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• Differential clock signals
• Meets SSTL_2 signal data
• Supports SSTL_2 class I specifications on outputs
• Low-voltage operation - VDD = 2.3V to 2.7V
• Available in 64 pin TSSOP and 56 pin MLF packages


Application

• DDR Memory Modules:
   - DDRI (PC1600, PC2100)
   - DDR333 (PC2700)
   - DDRI-400 (PC3200)
• Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857
• SSTL_2 compatible data registers


Pinout

Connection Diagram


Specifications

Storage Temperature.................. 65°C to +150°C
Supply Voltage ......................... -0.5 to 3.6V
Input Voltage1 ....................... -0.5 to VDD +0.5
Output Voltage1,2.....................-0.5 to VDDQ +0.5
Input Clamp Current.........................±50 mA
Output Clamp Current ........................±50 mA
Continuous Output Current .....................±50 mA
VDD, VDDQ or GND Current/Pin .................. ±100 mA
Package Thermal Impedance3 ................... 55°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Notes:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V0 >VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.


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