Features: • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• Supports LVCMOS switching levels on CSR# and RESET# inputs
• Low voltage operation VDD = 1.7V to 1.9V
• Available in 96 BGA package
Application• DDR2 Memory Modules
• Provides complete DDR DIMM logic solution with ICS97U877Pinout
SpecificationsStorage Temperature . . . . . . . . . . . . . 65 to +150
Supply Voltage . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V
Input Voltage1 . . . . . . . . . . . . . . . . -0.5 to VDD + 2.5V
Output Voltage1,2 . . . . . . . . . . . . . -0.5 to VDDQ + 0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50mA
Continuous Output Current . . . . . . . . . . . . . . . ±50mA
VDDQ or GND Current/Pin . . . . . . . . . . . . . . . ±100mA
Package Thermal Impedance3 . . . . . . . . . . . . . . . 36
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V0 >VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.DescriptionThis 25-bit 1:1 or 14-bit 1:2 configurable registered buffer of the ICSSSTU32864 is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. Alloutputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTU32864 operates
from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low.
The C0 input of the ICSSSTU32864 controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
The ICSSSTU32864 supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RST# must be held in the low state during power up.
In the DDR-II RDIMM application of the ICSSSTU32864, RST# is specified to be completely asynchronous with respect to CK and CK#.Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until the input receivers are fully enabled, the design of the ICSSSTU32864 must ensure that the outputs will remain low,thus ensuring no glitches on the output.
The ICSSSTU32864 monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS#
and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST inputhas priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is notdesired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
ICSSSTU32864 Data Sheet
