ICSSSTUA32S869B

Storage Temperature . . . . . . . . . .65°C to +150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . .   -0.5 to 2.5V
Input Voltage¹ . . . . . . . . . . . . . . . . -0.5 to VDD + 2.5V
Output Voltage^1,2 . . . . . . . . . . . . .  -0.5 to VDDQ + 0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50mA
Continuous Output Current . . . . . . . . . . . . . . . ±50mA
VDDQ or GND Current/Pin . . . . . . . . . . . . . . .  ±100mA
Package Thermal Impedance³. . . . . . . . . . . . . . . 36°C
Notes:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V₀ >V_DDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above  hose listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating  onditions for extended periods may affect product reliability.

The ICSSSTUA32S869B is 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation.All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers optimized to drive the DDR2 DIMM load. They provide 50% more dynamic driver strength than the standard SSTU32864 outputs.

The ICSSSTUA32S869B operates from a differential clock (CK and CK). Data are registered at the crossing of CK going
high, and CK going low.

The ICSSSTUA32S869B supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR1# are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK.Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.

ICSSSTUA32S869B must ensure that the outputs remain low as long as the data inputs are low, the clock is stable during the time from the low-to-high transition of RESET and the input receivers are fully enabled. This will ensures that there are no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn, PPO1 (Paritial-Parity-Out) and PTYERR1# (Parity Error) Parity outputs from changing states when both DCS and CSR are high. If either DCS or CSR input is low, the Qn, PPO1 and PTYERR1# outputs will function normally. The RESET input has priority over the DCS and CSR controls and will force the Qn and PPO outputs low and the PTYERR1# high.

The ICSSSTUA32S869B includes a parity checking function. The ICSSSTUA32S869B accepts a parity bit from the memory controller at its input pin PARIN1 one or two cycles after the corresponding data input, compares it with the data received on the D-inputs and indicates on its opendrain PTYERR1 pin (active low) whether a parity error has occurred. The number of cycles depends on the setting of C1, see Figure 6 and 7.

When used as a single device, the C1 input of the ICSSSTUA32S869B is tied low. When used in pairs, the C1 inputs is tied low for the first register (front) and the C1 input is tied high for the second register. When used as a single register, the PPO1 and PTYERR1#signals are produced two clock cycles after the corresponding data input. When used in pairs, the PTYERR1# signals of the first register are left floating. The PPO1 outputs of the first register are cascaded to the PARIN1 signals on the second register (back). The PPO1 and PTYERR1# signals of the second register are produced three clock cycles after the corresponding data input. Parity implimentation and device wiring for single and dual die is described in Figure 1. If an error occurs, and the PTYERR1# is driven low, it stays low for two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, CSR and DODT) of the ICSSSTUA32S869B are not included in the parity check computations.
All registers used on an individual DIMM must be of the same configuration, i.e single or dual die.