ICSSSTVA16857

Storage Temperature . . . . . . . . . . . ... . ... . 65 to +150
Supply Voltage . . . . . . . . . . . . . . . . .. . . . . . . . . -0.5 to 3.6V
Input Voltage¹ . . . . . . . . . . . . . . . . .. . . . . -0.5 to V_DD +0.5
Output Voltage^1,2 . . . . . . . . . . . . . . .. . . -0.5 to V_DDQ +0.5
Input Clamp Current . . . . . . . . . . . . .. . . ......... . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . .......... . . . . . . ±50 mA
Continuous Output Current . . . . . . . . .......... . . . . . . ±50 mA
V_DD, V_DDQ or GND Current/Pin . . . . . . . .......... . . . . ±100 mA
Package Thermal Impedance3 . . . . . . . . ..... . . . . . . . 55/W

Notes:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V₀ >V_DDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.

The 14-bit ICSSSTVA16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels,except for the LVCMOS RESET# input.

Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVA16857 supports low-power standby operation. A logic level "Low" at RESET# assures that all internal registers and outputs (Q) are reset to the logic "Low" state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up.

To ensure that outputs of the ICSSSTVA16857 are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic"Low" level during power up.

In the DDR DIMM application of  the ICSSSTVA16857, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,the register will be cleared and the outputs will be driven to a logic "Low" level quickly relative to the time to disable the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power standby state, the register of the ICSSSTVA16857 will become active quickly relative to the time to enable the differential input receivers. When the data inputs are at a logic level "Low" and the clock is stable during the "Low"-to-"High" transition of RESET# until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic "Low" level.