Features: • Differential clock signals
• Meets SSTL_2 signal data
• Supports SSTL_2 class II specifications on outputs
• low-voltage operation
- VDD = 2.3V to 2.7V
• Available in 64 pin TSSOP and 56 pin MLF2 packagesApplication·DDR Memory ModulesPinout
SpecificationsStorage Temperature . . . . . . . . . . 65°C to +150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input Voltage1 . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5
Output Voltage1,2 . . . . . . . . . . . . . . -0.5 to VDDQ +0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50mA
Continuous Output Current . . . . . . . . . . . . . . . ±50mA
VDD, VDDQ or GND Current/Pin . . . . . . . . . . . . ±100mA
Package Thermal Impedance3. . . . . . . . . . . . .. 55°C/W
Notes:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V0 >VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.DescriptionThe 13-bit to 26-bit ICSSSTV16859 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for the RESET# input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and clock are switched off.
The ICSSSTV16859 supports low-power standby operation. When RESET# is LOW, the differential input receivers are disabled, and are allowed. In addition, when RESET# is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET# input must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the LOW state during power up.
In the DDR DIMM application RESET# of the ICSSSTV16859 is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering RESET#, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of RESET#, the register will become active quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock is stable, during the time from the LOW-to-HIGH transition of RESET# until the input receivers of the ICSSSTV16859 are fully enabled, the design must ensure that the outputs will remain LOW.
ICSSSTV16859 Data Sheet
