Features: • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• Supports LVCMOS switching levels on CSR and RESET inputs
• Low voltage operation VDD = 1.7V to 1.9V
• Available in 96 BGA package
• Drop-in replacement for ICSSSTUA32864
• Green packages availableApplication• DDR2 Memory Modules
• Provides complete DDR DIMM solution with ICS97ULP877
• Ideal for DDR2 667, and 800Pinout
SpecificationsStorage Temperature . . . . . . . . . . . . 65 to +150
Supply Voltage . . . . . . . . . . . . . . . . . .. . .-0.5V to 2.5V
Input Voltage1,2 . . . . . . . . . . . . . . . . .. -0.5V to +2.5V
Output Voltage1,2 . . . . . . . . . . . -0.5V to VDD + 0.5V
Input Clamp Current . . . . . . . . . . . . . . . . . .. ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . ±50mA
Continuous Output Current. . . . . . . . . . . . . . . ±50mA
VDD or GND Current/Pin . . . . . . . . . . . . . . . . ±100mA
Package Thermal Impedance3 . . . . . . . . . . . . . .. 36
Notes:
1. The input and output negative voltageratings may be excluded if the input and output clamp ratings are observed.
2. This value is limited to 2.5V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DescriptionThis 25-bit 1:1 or 14-bit 1:2 configurable registered buffer of the ICSSSTUBF32866A is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUBF32866A operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
ICSSSTUBF32866A Data Sheet
