Features: • 28-bit 1:1 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• Supports LVCMOS switching levels on RESET input
• 50% more dynamic driver strength than standard SSTU32864
• Low voltage operation VDD = 1.7V to 1.9V
• Available in 96 BGA packageApplication• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A
• Optimized for DDR2 400/533/667 JEDEC 4 Rank VLP DIMMSPinout
SpecificationsStorage Temperature . . . . . . . . . . . . . . . . . . . . 65to +150
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V
Input Voltage1, . . . . . . . . . . . . . . . . . . . . . . . .. -0.5V to VDD +2.5V
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDDQ + 0.5V
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . .. ±50mA
Continuous Output Current . . . . . . . . . . . . . . ±50mA
VDD or GND Current/Pin . . . . . . . . . . . . . . . . ±100mA
Package Thermal Impedance3 . . . . . . . . . .. . 36
Notes:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This value is limited to 2.5V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.DescriptionThis 28-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The ICSSSTUB32872A operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.
The ICSSSTUB32872A supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
In the DDR2 RDIMM application of the ICSSSTUB32872A, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the
register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the ICSSSTUB32872A must ensure that the outputs will remain low, thus ensuring no glitches on the output.
The ICSSSTUB32872A monitors bothDCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over theDCS0 and DCS1 control and will force the Qn outputs low and the PTYERR output high.
The ICSSSTU32872A includes a parity checking function. The ICSSSTUB32872A accepts a parity bit from memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
Package options include 96-ball Thin Profile Fine Pitch BGA (TFBGA, MO-TBD).
ICSSSTUB32872A Data Sheet
