ICSSSTUAF32869A

The ICSSSTUAF32869A is 14-bit 1:2 registered buffer with parity, designed for 1.7 V to 1.9 V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers optimized to drive the DDR2 DIMM load. They provide 50% more dynamic driver strength than the standard SSTU32864 outputs.

The ICSSSTUAF32869A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low.

The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (V_REF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level.

To ensure defined outputs of the ICSSSTUAF32869A from the register before a stable clock has been supplied, RESET must be held in the low state during power up.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK.

Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. ICSSSTUAF32869A must ensure that the outputs remain low as long as the data inputs are low, the clock is stable during the time from the low-to-high transition of RESET and the input receivers are fully enabled. This will ensures that there are no glitches on the output.

The ICSSSTUAF32869A monitors both DCS and CSR inputs and will gate the Qn, PPO (Paritial-Parity-Out) and PTYERR (Parity Error) Parity outputs from changing states when both DCS and CSR are high. If either DCS and CSR input is low, the Qn, PPO and PTYERR outputs will function normally. The RESET input has priority over the DCS and CSR controls and will force the Qn and PPO outputs low and the PTYERR high.

The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with the data received on the D-inputs and indicates on its opendrain PTYERR pin (active low) whether a parity error has occurred. The number of cycles depends on the setting of C1. When used as a single device, the C1 input is tied low.

When used in pairs, the C1 inputs of the ICSSSTUAF32869A is tied low for the first register (front) and the C1 input is tied high for the second register. When used as a single register, the PPO and PTYERR signals are produced two clock cycles after the corresponding data input. When used in pairs, the PTYERR signals of the first register are left floating. The PPO outputs of the first register are cascaded to the PARIN signas on the second register (back). The PPO and PTYERR signals of the second register are produced three clock cycles after the corresponding data input. Parity implimentation and device wiring for single and dual die is described in the diagram below.

If an error occurs, and the PTYERR of the ICSSSTUAF32869A is driven low, it stays low for two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, CSR and DODT) are not included in the parity check computations.

All registers used on an individual DIMM must be of the same configuration, i.e single or dual die.