Features: • Packaged in 16 pin narrow SOIC• Access to VCO input and feedback paths of PLL• VCO operating range up to 135 MHz (5V)• Able to lock MHz range outputs to kHz range inputs through use of external dividers• Output Enable tri-states outputs• Low skew out...
ICS673-01: Features: • Packaged in 16 pin narrow SOIC• Access to VCO input and feedback paths of PLL• VCO operating range up to 135 MHz (5V)• Able to lock MHz range outputs to kHz range...
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Parameter | Conditions | Minimum | Maximum | Units |
Supply voltage, VDD | Referenced to GND | 7 | V | |
Inputs and Clock Outputs | Referenced to GND | -0.5 | VDD+0.5 | V |
Ambient Operating Temperature | ICS673M-01 | 0 | 70 | °C |
Ambient Operating Temperature | ICS673M-01I | -40 | 85 | °C |
Soldering Temperature | Max of 20 seconds | 260 | °C | |
Storage temperature | -65 | 150 | °C |
The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of the other. Through the use of external reference and VCO dividers (easily implemented with the ICS674-01), the user can easily customize the clock to lock to a wide variety of input frequencies.
Included on the ICS673-01 are an Output Enable function that puts both outputs into a highimpedance state, as well as a Power Down feature that turns off the entire device.