Features: • Packaged in 16 pin SOIC• Clock inputs from 5 to 160 MHz (see page 2)• Patented PLL with the lowest phase noise• Output clocks up to 160 MHz at 3.3 V• 15 selectable on-chip multipliers• Power down mode available• Low phase noise: -124 dBc/Hz at ...
ICS670-01: Features: • Packaged in 16 pin SOIC• Clock inputs from 5 to 160 MHz (see page 2)• Patented PLL with the lowest phase noise• Output clocks up to 160 MHz at 3.3 V• 15 sel...
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Parameter |
Conditions |
Minimum |
Typical |
Maximum |
Unit |
Supply voltage, VDD |
Referenced to GND |
7 |
V | ||
Inputs and Clock Outputs |
Referenced to GND |
-0.5 |
VDD+0.5 |
V | |
Ambient Operating Temperature |
0 |
70 |
|||
Ambient Operating Temperature, Iversion |
Industrial temp |
-40 |
85 |
||
Soldering Temperature |
Max of 10 seconds |
260 |
|||
Storage temperature |
-65 |
150 |
The ICS670-01 is a high speed, low phase noise Zero Delay Buffer (ZDB) which integrates ICS' proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of ICS' ClockBlocks™ family, the zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs, giving the appearance of no delay through the device. There are two identical outputs on the chip. The FBCLK of the ICS670-01 should be used to connect to the FBIN. Each output has its own output enable pin.
The chip is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing offchip feedback paths, the ICS670-01 can eliminate the delay through other devices. The 15 different on-chip multipliers work in a variety of applications. For other multipliers, including fractional multipliers, see the ICS527.