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IC62LV1008L

Features: • Access times of 55, 70, 100 ns• CMOS Low power operation: ICC=15mA (typical)* operation ISB2=2A (typical)* standby• Low data retention voltage: 1.5V (min.)• Output Enable (OE) and Two Chip Enables (CE1, CE2) inputs for ease in applications• TTL compatible ...

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SeekIC No. : 004370415 Detail

IC62LV1008L: Features: • Access times of 55, 70, 100 ns• CMOS Low power operation: ICC=15mA (typical)* operation ISB2=2A (typical)* standby• Low data retention voltage: 1.5V (min.)• Outpu...

IC62LV1008L Data Sheet

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Part Number:
IC62LV1008L
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Access times of 55, 70, 100 ns
• CMOS Low power operation:
  ICC=15mA (typical)* operation
  ISB2=2A (typical)* standby
• Low data retention voltage: 1.5V (min.)
• Output Enable (OE) and Two Chip Enables
  (CE1, CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation:
- No clock or refresh reguired
• Single 2.7V-3.6V power supply
• Wafer level burn in test mode
• Available in the know good die form and
  48-pin 8*10mm TF-BGA
* Typical values are measured at VCC=3.0V, TA=25°C


Specifications

Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND 0.5 to Vcc + 0.5 V
VCC Vcc related to GND 0.3 to +4.0 V
TBIAS Temperature Under Bias 40 to +85 °C
TSTG Storage Temperature 65 to +150 °C
PT Power Dissipation 1 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.


Description

The IC62LV1008L is a low voltage, 1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using ICSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable ( WE) controls both writing and reading of the memory. The IC62LV1008L are available in know good die form and 48-pin 8*10mm TF-BGA.




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