Features: ·Access time : 70, 85, 120, 150ns·High-density design : 16Mbit Design·Battery internally isolated until power is applied·Industry-standard 36-pin 2,048K x 8 pinout·Unlimited write cycles·Data retention in the absence of VCC·5-years minimum data retention in absence of power·Automatic wri...
HMN2M8D: Features: ·Access time : 70, 85, 120, 150ns·High-density design : 16Mbit Design·Battery internally isolated until power is applied·Industry-standard 36-pin 2,048K x 8 pinout·Unlimited write cycles·D...
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PARAMETER |
SYMBOL |
RATING |
CONDITIONS |
DC voltage applied on VCC relative to VSS |
VCC |
-0.5V to 7.0V |
|
DC Voltage applied on any pin excluding VCC relative to VSS |
VT |
-0.5V to 7.0V |
|
Operating temperature |
TOPR |
0 to 70 |
Commercial |
-40 to 80 |
Industrial | ||
Storage temperature |
TSTG |
-55to 125 |
|
Temperature under bias |
TBIAS |
-40to 85 |
|
Soldering temperature |
TSOLDER |
260 |
For 10 second |
NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
The HMN2M8D Nonvolatile SRAM is a 16,777,216-bit static RAM organized as 2,097,152 bytes by 8 bits.
The HMN2M8D has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid.
The HMN2M8D uses extremely low standby current CMOS SRAM's, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM.