HMN28D

Features:

· Access time : 70, 85, 120 and 150ns
· High-density design : 2KByte Design
· Battery internally isolated until power is applied
· JEDEC standard 24-pin DIP Package
· Low-power CMOS
· Unlimited writes cycles
· Data retention in the absence of V_CC
· 10-years minimum data retention in absence of power
· Automatic write-protection during power-up/power-down cycles
· Data is automatically protected during power loss
· Conventional SRAM operation; unlimited write cycles





Pinout




Specifications

PARAMETER	SYMBOL	RATING	CONDITIONS
DC voltage applied on VCC relative to VSS	VCC	-0.3V to 7.0V
DC Voltage applied on any pin excluding VCC relative to VSS	VT	-0.3V to 7.0V	VT VCC+0.3
Operating temperature	TOPR	0 to 70
Storage temperature	TSTG	-40 to 70
Temperature under bias	TBIAS	-10 to 70
Soldering temperature	TSOLDER	260	For 10 second

NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
           Functional operation should be restricted to the Recommended DC Operating Conditions detailed in
           this data sheet.
           Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The HMN28D are 16,384-bit, fully static, nonvolatile SRAM's organized as 2,048 bytes by 8 bits. Each NVSRAM has a self-contained lithium energy source and control circuitry, which constantly monitors Vcc for an out-of tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and writes protection is unconditionally enabled to prevent data corruption. The HMN28D devices can be used in place of existing 2K x 8 SRAM's directly conforming to the popular byte wide 24-pin DIP standard. There is no  imit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.

The HMN28D uses extremely low standby current CMOS SRAM's, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM.