HMN2568D

Features:

· Access time : 70, 85, 120, 150 ns
· High-density design : 2Mbit Design
· Battery internally isolated until power is applied
· Industry-standard 32-pin 256K x 8 pinout
· Unlimited write cycles
· Data retention in the absence of VCC
·10-years minimum data retention in absence of power
· Automatic write-protection during power-up/power-down cycles
· Data is automatically protected during power loss
· Conventional SRAM operation; unlimited write cycles


Pinout




Specifications

PARAMETER	SYMBOL	TSOLDER	CONDITIONS
DC voltage applied on VCC relative to VSS	VCC	-0.3V to 7.0V
DC voltage applied on VCC relative to VSS	VT	-0.3V to 7.0V	VT VCC+0.3
Operating temperature	TOPR	0 to 70 -40 to 85	Commercial Industrial
Storage temperature	TSTG	-40 to 85
Temperature under bias	TBIAS	-10 to 70
Soldering temperature	TSOLDER	260	For 10 second

NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The HMN2568D Nonvolatile SRAM is a 2,097,152-bit static RAM organized as 262,144 bytes by 8 bits.

The HMN2568D has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid.

The HMN2568D uses extremely low standby current CMOS SRAM's, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM.