HM-6883

Features:

• This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50mW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . .2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 2 TTL Loads
• On-Chip Address Register


Pinout




Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . .  . . . . GND -0.3V to VCC +0.3V
Typical Derating Factor . . . . . . . . . . .1.5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1


Description

The HM-6508/883 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation.

On chip latches of HM-6508/883  are provided for address allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays.

The HM-6508/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.