HB52RD648DC-B

Features:

• Fully compatible with: JEDEC standard outline 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out) Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness) Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 133/100 MHz (max)
• LVTTL interface
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8
• 2 variations of burst sequence Sequential Interleave
• Programmable CE latency: 2/3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh Auto refresh Self refresh
• Low self refresh current: HB52RF648DC-xxBL (L-version)
                                        : HB52RD648DC-xxBL (L-version)


Specifications

Parameter	Symbol	Value	Unit	Note
Voltage on any pin relative to VSS	VT	0.5 to VCC + 0.5 ( 4.6 (max))	V	1
Supply voltage relative to VSS	VCC	0.5 to +4.6	V	1
Short circuit output current	IOUT	50	mA
Power dissipation	PT	8.0	W
Operating temperature	Topr	0 to +65
Storage temperature	Tstg	55 to +125

Description

The HB52RF648DC, HB52RD648DC are a 32M × 64 × 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 16 pieces of 256-Mbit SDRAM (HM5225805BTB) sealed in TCP package and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting possible without surface mount technology. HB52RF648DC, HB52RD648DC  provide common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board.