GS820V32T

• Single 3.3V +5%/-5% power supply
• Separate VDDQ to allow 2.375V to 3.465V output supply level
• High frequency operation: 117MHz
• Fast access time: 4.5ns Clock to Q
• Low power: 0.5mA ISB and IDD static
• FT mode pin for either flow-thru or pipeline operation
• LBO mode pin for linear or interleave (Pentium^TM and X86) burst mode
• Byte write (BWE) and global write (GW) operation
• 3 chip enable signals for easy depth expansion
• 2 cycles enable (pipeline mode) and 1 cycle disable to allow multiple bank without data buss contention
• Compatible to both 3.3V and 2.5V interface level
• Standard Industrial Temperature Option: -40 to + 85
• JEDEC standard 100 lead package:
         Q: QFP
         T: TQFP
Pentium is a trademark of Intel Corp.

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

The GS820V32 is a 64Kx32 high performance synchronous SRAM with 2 bit burst counter. GS820V32 is designed to provide L2 Cache for Pentium^TM and other high performance CPU. Addresses (A0-15), data IOs (DQ1-32), chip enables (CE1 , CE2, CE3), address control inputs (ADSP , ADSC, ADV) and write control inputs (BW1, BW2, BW3, BW4, BWE, GW) are synchronous and are controlled by a positive edge triggered clock (CLK).

Output enable (OE) and power down control of GS820V32 (ZZ) are asynchronous. 2 mode control pins (LBO & FT) define 4 operation modes of linear/interleave burst order and output flow thru/pipeline.

Burst GS820V32 can be initiated with either ADSP or ADSC inputs. Subsequent burst address are generated internally and are controlled by ADV. The burst sequence is either interleave order (Pentium^TM and X86) or linear order and is defined by LBO.

Output registers of GS820V32 are provided and are controlled by FT mode pin. With FT mode pin, Output registers can be programmed in either pipeline mode for very high frequency operation (117MHz) or flow-thru mode for reduced latency.

Byte write operation of GS820V32 can be obtained through byte write enable (BWE) input combined with 4 individual byte write signals BW1-4. In addition, global write (GW) signal is also available to write all bytes at once.

Low power state of GS820V32 (standby mode) can be obtained either through the assertion of ZZ signal or simply stop the clock (CLK). In standby mode, memory data are still retained. Low power design of 0.5mA standby are provided on L version.

The GS820V32 operates from a 3.3V power supply and all inputs and outputs are LVTTL compatible. Separate output power (VDDQ) and ground (VSSQ) pins are employed to decouple output noise from internal circuit and VDDQ allow user the flexibility to employ lower output supply level like 2.5V. GS820V32's interface level is also compatble to 2.5V supply level.

The GS820V32 is implemented with GSI's high performance CMOS technology and is available in JEDEC standard 100 lead QFP ( Q version ) and TQFP ( T version) package.