Features: •FT pin for user-configurable flow through or pipelined operation• Single Cycle Deselect (SCD) operation• 3.3 V +10%/5% core power supply• 2.5 V or 3.3 V I/O supply•LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins all...
GS82032AT: Features: •FT pin for user-configurable flow through or pipelined operation• Single Cycle Deselect (SCD) operation• 3.3 V +10%/5% core power supply• 2.5 V or 3.3 V I/O supply...
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Features: • Single Cycle Deselect (SCD) operation• 3.3 V +10%/5% core power supplyR...
Features: • FT • Single Cycle Deselect (SCD) operation• 3.3 V +10%/5% core power...
The GS82032A is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Symbol | Description | Value | Unit |
VDD | Voltage on VDD Pins | -0.5 to 4.6 | V |
VDDQ | Voltage in VDDQ Pins | -0.5 to VDD | V |
VCK | Voltage on Clock Input Pin | 0.5 to 6 | V |
VI/O | Voltage on I/O Pins | -0.5 to VDDQ+0.5 ( 4.6 V max.) | V |
VIN | Voltage on Other Input Pins | -0.5 to VDD+0.5 ( 4.6 V max.) | V |
IIN | Input Current on Any Pin | +/- 20 | mA |
IOUT | Output Current on Any I/O Pin | +/- 20 | mA |
PD | Package Power Dissipation | 1.5 | W |
TSTG | Storage Temperature | -55 to 125 | |
TBIAS | Temperature Under Bias | -55 to 125 |