GAL20V8 Selling Leads, Price trend, GAL20V8 DataSheet download, circuit diagram from SeekIC.com

Features: • HIGH PERFORMANCE E2 CMOS® TECHNOLOGY - 5 ns Maximum Propagation Delay - Fmax = 166 MHz - 4 ns Maximum from Clock Input to Data Output - UltraMOS® Advanced CMOS Technology• 50% to 75% REDUCTION IN POWER FROM BIPOLAR - 75mA Typ Icc on Low Power Device - 45mA Typ Icc o...

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SeekIC No. : 004347106 Detail

GAL20V8: Features: • HIGH PERFORMANCE E2 CMOS® TECHNOLOGY - 5 ns Maximum Propagation Delay - Fmax = 166 MHz - 4 ns Maximum from Clock Input to Data Output - UltraMOS® Advanced CMOS Technology&#...

GAL20V8 Data Sheet

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Part Number:: GAL20V8
Supply Ability:: 5000

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Product Details

Description

Features:

• HIGH PERFORMANCE E² CMOS^® TECHNOLOGY
   - 5 ns Maximum Propagation Delay
   - Fmax = 166 MHz
   - 4 ns Maximum from Clock Input to Data Output
   - UltraMOS^® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
   - 75mA Typ Icc on Low Power Device
   - 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E² CELL TECHNOLOGY
   - Reconfigurable Logic
   - Reprogrammable Cells
   - 100% Tested/100% Yields
   - High Speed Electrical Erasure (<100ms)
   - 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
   - Maximum Flexibility for Complex Logic Designs
   - Programmable Output Polarity
   - Also Emulates 24-pin PAL^® Devices with Full Function/ Fuse Map/
       Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
   - 100% Functional Testability
• APPLICATIONS INCLUDE:
   - DMA Control
   - State Machine Control
   - High Speed Graphics Processing
   - Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Pinout

Connection Diagram

Specifications

Supply voltage V_CC ....................................... 0.5 to +7V
Input voltage applied .......................... 2.5 to V_CC +1.0V
Off-state output voltage applied ......... 2.5 to V_CC +1.0V
Storage Temperature ................................... 65 to 150
Ambient Temperature with
Power Applied .............................................. 55 to 125

1.Stresses above those listed under the "Absolute Maximum Ratings"
   may cause permanent damage to the device. These are stress only
   ratings and functional operation of the device at these or at any
   other conditions above those indicated in the operational sections of
   this specification is not implied (while programming, follow the
   programming specifications).

Description

The GAL20V8C, at 5ns maximum propagation delay time, com- bines a high performance CMOS process with Electrically Eras- able (E²) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and ef- ficiently.

The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configura- tions possible with the GAL20V8 are the PAL
architectures listed in the table of the macrocell description section. GAL20V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.

Unique test circuitry and reprogrammable cells of GAL20V8 allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

GAL20V8

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