Features: • HIGH PERFORMANCE E2CMOS® TECHNOLOGY - 3.5 ns Maximum Propagation Delay - Fmax = 250 MHz - 2.5 ns Maximum from Clock Input to Data Output - UltraMOS® Advanced CMOS Technology - TTL-Compatible Balanced 8mA Output Drive• 3.3V LOW VOLTAGE 20V8 ARCHITECTURE - JEDEC-Compa...
GAL20LV8: Features: • HIGH PERFORMANCE E2CMOS® TECHNOLOGY - 3.5 ns Maximum Propagation Delay - Fmax = 250 MHz - 2.5 ns Maximum from Clock Input to Data Output - UltraMOS® Advanced CMOS Technolog...
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Features: • 3.3V LOW VOLTAGE, ZERO POWER OPERATION - JEDEC Compatible 3.3V Interface Standar...
SPLD - Simple Programmable Logic Devices 20 INPUT 10 OUTPUT 5 V LOW POWER 10ns
The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility.
Unique test circuitry and reprogrammable cells of GAL20LV8 allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.