GAL20RA10 Selling Leads, Price trend, GAL20RA10 DataSheet download, circuit diagram from SeekIC.com

Features: • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY - 7.5 ns Maximum Propagation Delay - Fmax = 83.3 MHz - 9 ns Maximum from Clock Input to Data Output - TTL Compatible 8 mA Outputs - UltraMOS® Advanced CMOS Technology• 50% to 75% REDUCTION IN POWER FROM BIPOLAR - 75mA Typical Icc...

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SeekIC No. : 004347105 Detail

GAL20RA10: Features: • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY - 7.5 ns Maximum Propagation Delay - Fmax = 83.3 MHz - 9 ns Maximum from Clock Input to Data Output - TTL Compatible 8 mA Outputs - UltraMO...

GAL20RA10 Data Sheet

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Part Number:: GAL20RA10
Supply Ability:: 5000

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Upload time: 2024/12/21

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Product Details

Description

Features:

• HIGH PERFORMANCE E2CMOS ^® TECHNOLOGY
   - 7.5 ns Maximum Propagation Delay
   - Fmax = 83.3 MHz
   - 9 ns Maximum from Clock Input to Data Output
   - TTL Compatible 8 mA Outputs
   - UltraMOS^® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
   - 75mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS
• E² CELL TECHNOLOGY
   - Reconfigurable Logic
   - Reprogrammable Cells
   - 100% Tested/100% Yields
   - High Speed Electrical Erasure (<100 ms)
   - 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
   - Independent Programmable Clocks
   - Independent Asynchronous Reset and Preset
   - Registered or Combinatorial with Polarity
   - Full Function and Parametric Compatibility with PAL20RA10
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
   - 100% Functional Testability
• APPLICATIONS INCLUDE:
   - State Machine Control
   - Standard Logic Consolidation
   - Multiple Clock Logic Designs
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Pinout

Connection Diagram

Specifications

Supply voltage V_CC ........................................ -0.5 to +7V
Input voltage applied ........................... -2.5 to V_CC+1.0V
Off-state output voltage applied .......... -2.5 to V_CC +1.0V
Storage Temperature .................................... -65 to 150
Ambient Temperature with
   Power Applied ............................................ -55 to 125

1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to
   the device. These are stress only ratings and functional operation of the device at these or at any other
   conditions above those indicated in the operational sections of this specification is not implied (while
   programming, follow the programming specifications).

Description

The GAL20RA10 combines a high performance CMOS process with electrically erasable (E²) floating gate technology to provide the highest speed performance available in the PLD market. Lattice Semiconductor's E²CMOS circuitry achieves power levels as low as 75mA typical I_CC which represents a substantial savings in power when compared to bipolar counterparts. E² technology offers high speed (<100ms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.

The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL20RA10 is a direct parametric compatible CMOS replacement for the PAL20RA10 device.

Unique test circuitry and reprogrammable cells of GAL20RA10 allow complete AC, DC, and functional testing during manufacturing. Therefore, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

GAL20RA10

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