FMS7951

Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only.

Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may effect reliability.

FMS7951 is a high speed, zero delay, low skew clock driver. It uses phase locked loop technology to generate frequencies up to 175 MHz.

FMS7951 has four banks of configurable outputs. By externally connecting one of the outputs to FBIN, the internal PLL will lock in both phase and frequency to the incoming clock. Any changes to the input clock will be tracked by the outputs.

Depending on the selected output for feedback connection, the output frequencies of FMS7951 will be as 1X, 2X or 4X of the input.

REF_SEL allows selection between PECL input or TCLK a CMOS clock driven input. Connecting PLL_EN LOW and REF_SEL HIGH will by pass the Phase locked loop. In this mode, FMS7951 will be in clock buffer mode where any clock applied to TCLK will be divided down to the four output banks. This is ideal for system diagnostic test. When PLL_EN is HIGH, the PLL is enabled, and any clock applied to TCLK will be locked in both phase and frequency to FBIN. PECL_CLK is activated when REF_SEL is high.

FMS7951 operates at 3.3 Volts and is available in 32 pin LQFP.