FMS7950

Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only.

Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may effect reliability.

FMS7950 is a high speed clock synthesizer designed for clock multiplication applications. It uses phase locked loop technology to generate frequencies up to 175 MHz. It has four banks of configurable outputs.

Feedback select (FBsel) pin allows for wider range of input frequencies. When connected low, the lower input frequency range is selected. FMS7950 provides output frequencies of up to eight times the input (see table 3). The higher input range is allowed when FBsel is connected high.

There are four banks of outputs of FMS7950 where each bank has a dedicated divide select (DIV_SEL). Depending on the divide selection, the outputs are one half, one quarter, or one eighth of the VCO speed (see table 2 for details).

REF_SEL allows selection between crystal input or a clock driven input. Connecting PLL_EN LOW and REF_SEL HIGH will disable the Phase locked loop when the crystal oscillator is not used. In this mode, FMS7950 will be in clock buffer mode where any clock applied to TCLK will be divided down to the four output banks per Table 2. This is ideal for system diagnostic test.

FMS7950 operates at 3.3 Volts and is available in 32 pin LQFP.