Position: Home  > All Categories> Integrated Circuits (ICs) > EDD5116ADTA-5C

EDD5116ADTA-5C

Features: * Power supply: VDD ,VDDQ = 2.6V ± 0.1V * Data rate: 400Mbps (max.) * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized...

product image

EDD5116ADTA-5C Picture
See larger image
SeekIC No. : 004333783 Detail

EDD5116ADTA-5C: Features: * Power supply: VDD ,VDDQ = 2.6V ± 0.1V * Data rate: 400Mbps (max.) * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional data strobe (DQS) is transmitted /r...

EDD5116ADTA-5C Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
EDD5116ADTA-5C
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/12/26

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

* Power supply:  VDD ,VDDQ = 2.6V ± 0.1V
* Data rate: 400Mbps (max.)
* Double Data Rate architecture; two data transfers per clock cycle 
* Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver 
* Data inputs, outputs, and DM are synchronized with DQS
* 4 internal banks for concurrent operation
* DQS is edge aligned with data for READs; center aligned with data for WRITEs
* Differential clock inputs (CK and /CK)
* DLL aligns DQ and DQS transitions with CK transitions
* Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
* Data mask (DM) for write data
* Auto precharge option for each burst access
* SSTL_2 compatible I/O
* Programmable burst length (BL):  2, 4, 8
* Programmable /CAS latency (CL): 3
* Programmable output driver strength: normal/weak
* Refresh cycles:  8192 refresh cycles/64ms 
- 7.8s maximum average periodic refresh interval
* 2 variations of refresh 
- Auto refresh  
- Self refresh 


Pinout

Connection Diagram


Specifications

Parameter Symbol Rating Unit Note
Voltage on any pin relative to VSS VT -1.0 to +3.6 V  
Supply voltage relative to VSS VDD -1.0 to +3.6 V  
Short circuit output current IOS 50 mA  
Power dissipation PD 1.0 W  
Operating ambient temperature TA 0 to +70    
Storage temperature Tstg -55 to +125    



Description

The EDD5108AD and the EDD5116AD are 512M bits Double Data Rate (DDR) SDRAM, organized as 16,777,216 words × 8 bits × 4 banks and 8,388,608 words × 16 bits × 4 banks, respectively.

Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer EDD5108AD and the EDD5116AD is realized by the 2 bits prefetch-pipelined architecture.  Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. They are packaged in standard 66-pin plastic TSOP(II).




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Kits
IT243
UVSC-110-4E1
Industrial Controls, Meters
SGDM-15ADA
41AA1600E
Test Equipment
TOP853
TOP2005
Tools
TCP202
G084SN05 V.3
Sensors, Transducers
GP2Y0D340K
PAN3509DH-TXWA
Programmers, Development Systems
ARDUINO IIC/I2C 液晶模块
JTAG-SMT2
View more