EDD5104ADTA

Features:

Power supply:  VDD, VDDQ = 2.5V ± 0.2V
Data Rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per clock cycle 
Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver 
Data inputs, outputs, and DM are synchronized with DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL):  2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Programmable output driver strength: normal/weak
Refresh cycles:  8192 refresh cycles/64ms
   -7.8s maximum average periodic refresh interval 
2 variations of refresh
   -Auto refresh 
   -Self refresh


Pinout




Specifications

Parameter	Symbol	Rating	Unit	Note
Voltage on any pin relative to VSS	VT	-1.0 to +3.6	V
Supply voltage relative to VSS	VDD	-1.0 to +3.6	V
Short circuit output current	IOS	50	mA
Power dissipation	PD	1.0	W
Operating ambient temperature	TA	0 to +70	°C
Storage temperature	Tstg	-55 to +125	°C

Description

The EDD5104AD, the EDD5108AD and the EDD5116AD are 512M bits Double Data Rate (DDR) SDRAM.  Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer EDD5104AD, the EDD5108AD and the EDD5116AD is realized by the 2 bits prefetch-pipelined architecture.  Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.  It is packaged in standard 66-pin plastic TSOP (II).