EDD5104ABTA

Features:

2.5 V power supply:  VDDQ = 2.5V ± 0.2V
                                 :  VDD = 2.5V ± 0.2V
Data Rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers pe clock cycle 
Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver 
Data inputs, outputs, and DM are synchronized with DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
2.5 V (SSTL_2 compatible) I/O
Programmable burst length (BL):  2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles:  8192 refresh cycles/64ms
   -7.8s maximum average periodic refresh interval
2 variations of refresh 
   -Auto refresh 
   -Self refresh 


Pinout




Specifications

Parameter	Symbol	Rating	Unit	Note
Voltage on any pin relative to VSS	VT	-1.0 to +3.6	V
Supply voltage relative to VSS	VDD	-1.0 to +3.6	V
Short circuit output current	IOS	50	mA
Power dissipation	PD	1.0	W
Operating ambient temperature	TA	0 to +70	°C
Storage temperature	Tstg	-55 to +125	°C

Description

The EDD5104AB is a 512M bits Double Data Rate (DDR) SDRAM organized as 33,554,432 words × 4 bits × 4 banks.  The EDD5108AB is a 512M bits DDR SDRAM organized as 16,777,216 words × 8 bits × 4 banks.  Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer EDD5104AB is realized by the 2 bits prefetch-pipelined
architecture.  Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) can be set enable or disable. They are packaged in standard 66-pin plastic TSOP (II)10.16mm(400).