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EDD5108AFTA

Features: Power supply: VDD, VDDQ = 2.5V ± 0.2V Data Rate: 333Mbps/266Mbps (max.) Double Data Rate architecture; two data transfers per clock cycle Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver Data inputs, outputs, and DM are synchronized w...

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SeekIC No. : 004333779 Detail

EDD5108AFTA: Features: Power supply: VDD, VDDQ = 2.5V ± 0.2V Data Rate: 333Mbps/266Mbps (max.) Double Data Rate architecture; two data transfers per clock cycle Bi-directional data strobe (DQS) is transmitted /r...

EDD5108AFTA Data Sheet

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Part Number:
EDD5108AFTA
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

Power supply:  VDD, VDDQ = 2.5V ± 0.2V
Data Rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per clock cycle 
Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver 
Data inputs, outputs, and DM are synchronized with DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL):  2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Programmable output driver strength: normal/weak
Refresh cycles:  8192 refresh cycles/64ms
   -7.8s maximum average periodic refresh interval 
2 variations of refresh 
   -Auto refresh 
   -Self refresh
TSOP (II) package with lead free solder (Sn-Bi)
   -RoHS compliant


Pinout

Connection Diagram


Specifications

Parameter Symbol Rating Unit Note
Voltage on any pin relative to VSS VT -1.0 to +3.6 V  
Supply voltage relative to VSS VDD -1.0 to +3.6 V  
Short circuit output current IOS 50 mA  
Power dissipation PD 1.0 W  
Operating ambient temperature TA 0 to +70 °C  
Storage temperature Tstg -55 to +125 °C  



Description

The EDD5108AFTA and the EDD5116AFTA are 512M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words × 8 bits × 4 banks and 8,388,608 words × 16 bits × 4 banks, respectively.  Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer EDD5108AFTA and the EDD5116AFTA is realized by the 2 bits prefetch-pipelined architecture. 
Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.  It is packaged in standard 66-pin plastic TSOP (II).


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