EDD5108AFTA-5

• Power supply:  VDD ,VDDQ = 2.6V ± 0.1V
• Data rate: 400Mbps (max.)
• Double Data Rate architecture; two data transfers per clock cycle 
• Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver 
• Data inputs, outputs, and DM are synchronized with DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL):  2, 4, 8
• Programmable /CAS latency (CL): 3
• Programmable output driver strength: normal/weak
• Refresh cycles:  8192 refresh cycles/64ms  7.8µs maximum average periodic refresh interval
• 2 variations of refresh  Auto refresh   Self refresh 
• TSOP (II) package with lead free solder (Sn-Bi)  RoHS compliant

The EDD5108AFTA and the EDD5116AFTA are 512M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words × 8 bits × 4 banks and 8,388,608 words × 16 bits × 4 banks, respectively.  Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer EDD5108AFTA and the EDD5116AFTA is realized by the 2 bits prefetch-pipelined architecture.  Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.  They are
packaged in standard 66-pin plastic TSOP (II).