DS38C86A

The DS38C86A is a 9-bit BTL Latching Data Transceiver designed specifically for proprietary bus interfaces. The device is implemented in CMOS technology, and delivers all of the performance of its Bi-CMOS counterparts while consuming less then half of the power supply current of the DS3886A. The DS38C86A conforms to the IEEE 11941.1 (Backplane Transceiver Logic - BTL) Standard.

The DS38C86A incorporates an edge-triggered latch in the driver path which can be bypassed during fall-through mode of operation and a transparent latch in the receiver path. The DS38C86A driver output configuration is an open drain which allows Wired-OR connection on the bus. A unique design reduces the bus loading to 3 pF typical. The driver also has high sink current capability to comply with the bus loading requirements defined within IEEE 11941.1 BTL specification.

Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semiconductor, then developed by the IEEE to enhance the performance of backplane buses. BTL transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum noise immunity.

The BTL standard eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to a 2.1V at both ends. The low voltage is typically 1V. The DS38C86A provides an alternative to high power Bipolar and BiCMOS devices with the use of CMOS technology.

The CMOS technology enables the DS38C86A to operate at 50% of the ICC required by the Bi-CMOS DS3886A. This can have a major impact on system power consumption. For example, if a backplane is 128 bits wide, 16 devices (9 bits each) required per card. Also assume the backplane is one rack with 20 slots. Power dissipation savings for this application is calculated by the following equation: P = ICC-savings x Power supply voltage x number of devices P = 32 mA x 5.5V x 320 = 56 Watts

The power dissipation savings may increase even more when; the system bus is wider than 128 bits, there are multiple racks in the system, or if the system includes a hot backup. This may double the power dissipation savings. Separate ground pins are provided for each BTL output minimize induced ground noise during simultaneous switching. The unique driver circuitry provides a maximum slew rate of 0.9V/ns which allows controlled rise and fall times to reduce noise coupling to adjacent lines. The transceiver's high impedance control and driver inputs are fully TTL compatible.

The receiver is a high speed comparator that utilizes a Bandgap reference for precision threshold control allowing maximum immunity to the BTL 1V signaling level. Separate QVCC and QGND pins are provided to minimize the effects of high current switching noise. The receiver output is TRI-STATE® and fully TTL compatible.

The DS38C86A supports live insertion as defined in IEEE 896.2 through the LI (Live Insertion) pin. To implement live insertion the LI pin should be connected to the live insertion power connector. If this function is not supported, the LI pin must be tied to the VCC pin. The DS38C86A also provides glitch free power up/down protection during power sequencing.

The DS38C86A has two types of power connections in addition to the LI pin. They are the Logic VCC (VCC) and the Quiet VCC (QVCC). There are two Logic VCC pins on the DS38C86A that provide the supply voltage for the logic and control circuitry. Multiple connections are provided to reduce the effects of package inductance and thereby minimize switching noise. A voltage delta between VCC and QVCC should never exceed ±0.5V because of ESD circuitry. When CD (Chip Disable) is high, An is in high impedance state and Bn is high. To transmit data (An to Bn), the T/R signal is high.

When RBYP is high, the positive edge triggered flip-flop is in the transparent mode. When RBYP is low, the positive edge of the ACLK signal clocks the data. In addition, the ESD circuitry between the VCC pins and all other pins except for BTL I/O's and LI pins requires that any voltage on these pins should not exceed the voltage on VCC +0.5V.

There are three different types of ground pins on the DS38C86A; the logic ground (GND), BTL grounds (B0GNDB8GND) and the Bandgap reference ground (QGND). All of these ground reference pins are isolated within the chip to minimize the effects of high current switching transients. For optimum performance the QGND should be returned to the connector through a quiet channel that does not carry transient switching current. The GND and B0GNDB8GND should be connected to the nearest backplane ground pin with the shortest possible path.

Since many different grounding schemes could be implemented and ESD circuitry exists on the DS38C86A, it is important to note that any voltage between ground pins, QGND, GND or B0GNDB8GND should not exceed ±0.5V including power up/down sequencing.

The DS38C86A is offered in a 48-pin 7 x 7 space saving PQFP package.