DS3885

Features: 9-bit inverting BTL transceiver Meets IEEE 1194.1 standard on Backplane TransceiverLogic (BTL) Includes on chip competition logic and parity checking Supports live insertion Glitch free power-up/down protection Typically less than 5 pF bus-port capacitance Low bus-port voltage swing (typ...

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SeekIC No. : 004329073 Detail

DS3885: Features: 9-bit inverting BTL transceiver Meets IEEE 1194.1 standard on Backplane TransceiverLogic (BTL) Includes on chip competition logic and parity checking Supports live insertion Glitch free po...

floor Price/Ceiling Price

Part Number:
DS3885
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

 9-bit inverting BTL transceiver
Meets IEEE 1194.1 standard on Backplane TransceiverLogic (BTL)
Includes on chip competition logic and parity checking
Supports live insertion
Glitch free power-up/down protection
Typically less than 5 pF bus-port capacitance
Low bus-port voltage swing (typically 1V) at 80 mA
Open collector bus-port output allows Wired-ORconnection
Exceeds 2 kV ESD testing (Human Body Model)
Individual bus-port ground pins minimize ground bounce
Controlled rise and fall time to reduce noise coupling toadjacent lines
TTL compatible driver and control inputs
Built in bandgap reference with separate QVCC andQGND pins for precise receiver thresholds
Product offered in PLCC and PQFP package styles



Pinout

  Connection Diagram




Specifications

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage ..................................................6.5V
Control Input Voltage .......................................6.5V
Driver Input and Receiver Output ...................  5.5V
Receiver Input Current................................±15 mA
Bus Termination Voltage ..................................2.4V
Power Dissipation at 25 PLCC..................  .. 2.5W
PQFP............................................................... 1.3W
Derate PLCC Package ..............................20 mW/
Derate PQFP Package ...........................11.1 mW/
Storage Temperature Range ..........65to a150
Lead Temperature (Soldering, 4 sec.) ............260
 


Description

The DS3885 is one in a series of transceivers designed spe-cifically for the implementation of high performance Future-busa and proprietary bus interfaces. The DS3885 Arbitra-tion Transceiver is designed to conform to IEEE 1194.1(Backplane Transceiver LogicÐBTL) as specified in theIEEE 896.2 Futurebusa specification. The ArbitrationTransceiver incorporates the competition logic internallywhich simplifies the implementation of a Futurebusa appli-cation by minimizing the on board logic required.

The DS3885 driver output configuration is an NPN open col-lector which allows Wired-OR connection on the bus. Eachdriver output incorporates a Schottky diode in series with itscollector to isolate the transistor output capacitance fromthe bus thus reducing the bus loading in the inactive state.The BTL drivers also have high sink current capability tocomply with the bus loading requirements defined withinIEEE 1194.1 BTL specification.Backplane Transceiver Logic (BTL) is a signaling standardthat was invented and first introduced by National Semicon-




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